开发工具/系统

方案关键器件表：

型号	品牌	产品描述	类型
Cadence SiP Layout	Cadence	Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die, side by side die, and stacked die designs and also provides the foundation for chip-package co-design with Encounter or Virtuoso.	IC 封装和SiP设计
Cadence Space-Based Router	Cadence	Offers the performance and capacity to handle designs with growing complexity and increasing digital and analog/mixed-signal content.	定制IC设计
Cadence SpeedBridge Adapters	Cadence	将全速设备接口直接与设计连接，并以仿真速度运行。支持在真实世界工作条件下的电路仿真。能过外部数据--激励和响应的真实性来确保仿真器中设计系统行为的正确性，从而降低产品的设计风险	系统设计与验证
Cadence VIP Catalog	Cadence	该Cadence VIP产品提供了业界最广泛的复杂协议验证IP选择，其中包括超过15,000内存模型	功能验证
Cadence Virtuoso SiP Architect	Cadence	Delivers a single schematic and simulation solution for RF/analog ICs and complex IC package substrates. Supports package substrate-level passive structures based on Pcell technology. Also enables chip-package co-design with Virtuoso.	IC 封装和SiP设计
C-to-Silicon Compiler	Cadence	新一代的高阶综合技术，能从有时序或无时序的C/C++/SystemC自动生成可综合的高质量的RTL代码—无论是面积还是性能上都能满足客户需求。	系统设计与验证
Encounter Conformal Constraint Designer	Cadence	Automates the validation and refinement of constraints to ensure that timing constraints are valid throughout the entire design process. Identifies issues with clock-domain crossings early in the design process, helping designers achieve convergence on de	逻辑设计
Encounter Conformal ECO Designer	Cadence	Combines automatic ECO analysis, ECO logic optimization, and design netlist modification with the industry’s most trusted equivalence checking solution. Brings greater automation, predictability, and design convergence to pre- and post-mask ECOs.	逻辑设计
Encounter Conformal Equivalence Checker	Cadence	Handles large, complex datapaths, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs semantic and RTL linting checks.	逻辑设计
Encounter Conformal Low Power	Cadence	Enables the creation and validation of power intent in context of the design. Combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs.	逻辑设计
Encounter DFT Architect	Cadence	Minimizes test development and production costs. Delivers a flexible compression solution plus an integrated, power-aware methodology for specifying, inserting, and verifying full-chip production tests.	逻辑设计
Encounter Diagnostics	Cadence	Delivers the most accurate volume and precision diagnostics capability available on the market. Accelerates silicon bring-up and optimizes yield ramp with device and fault modeling.	可制造性签收
Encounter Digital Implementation System	Cadence	无论是针对giga-gate/GHz、低功耗还是混合信号设计，无论是主流工艺节点还是先进工艺节点，都提供一个完整的单一设计平台并支持多CPU的解决方案。	数字实现
Encounter Digital Implementation System	Cadence	无论是针对giga-gate/GHz、低功耗还是混合信号设计，无论是主流工艺节点还是先进工艺节点，都提供一个完整的单一设计平台并支持多CPU的解决方案。	定制IC设计
Encounter Digital Implementation System	Cadence	无论是针对giga-gate/GHz、低功耗还是混合信号设计，无论是主流工艺节点还是先进工艺节点，都提供一个完整的单一设计平台并支持多CPU的解决方案。	可制造性签收
Encounter Library Characterizer	Cadence	自动生成最新建模格式的库，加速表征和重新定性。	数字实现
Encounter Power System	Cadence	在整个设计与实现流程中提供了一致的、收敛的功耗与电源轨道完整性分析——跨越布图规划、电源规划、物理实现、优化与签收。它不仅帮助前端逻辑设计师获得高质量的、简单的与早期的功耗和电源轨道分析，而且帮助后端物理工程师实现全面的签收分析与晶片关联。.	数字实现
Encounter RTL Compiler	Cadence	Allows engineers to concurrently optimize timing, area, power, and signal integrity intent. Offers a unique set of patented global-focus algorithms and physically-aware layout estimation capability.	逻辑设计
Encounter RTL Compiler with Physical	Cadence	Enables logic designers to account for physical interconnect—-without the need to learn how to do physical design.	逻辑设计
Encounter Timing System	Cadence	Serves both front-end logic designers looking for high-quality static timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff.	逻辑设计

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