Benefits

• Provides faster turnaround time by minimizing manual intervention and eliminating time-consuming iterations
• Generates early estimates on ECO feasibility by quantifying designer intent
• Implements complex ECOs that are typically not attempted manually
• Enables front-end designers in fabless semiconductor companies earlier netlist handoff to ASIC vendors
• Improves designer productivity and offers flexibility to do ECO with metal-only layers, thus reducing manufacturing costs and driving faster design convergence toward tapeout
• Reduces verification time significantly by using abstraction techniques to verify multi-million–gate designs much faster than traditional gate-level simulation
• Decreases the risk of missing critical bugs through independent verification technology