Part of the Encounter Test family, Encounter Diagnostics offers a comprehensive solution for silicon bring-up and debug with advanced fault modeling to boost productivity and predictability, reduce development costs, and accelerate time to market. It offers an industry-leading 80-100% defect identification rate as verified by physical failure analysis.

Encounter Diagnostics supports volume and precision operating modes, static and dynamic diagnostics, patented pattern fault modeling, schematic cross-probing between logic and physical models, and all industry-standard automated test pattern generation (ATPG) test vector formats.



In volume mode, Encounter Diagnostics uses advanced statistical analysis with an SQL-compatible database to analyze diagnostic callouts, and it uses failure data to identify the primary yield-limiting issues. Volume analysis supports both logic and physical attributes. In precision mode, it pinpoints nanometer defects using capabilities such as scan-chain diagnostics, advanced callout analysis, diagnostics test pattern generation, invariant analysis, and an advanced integrated GUI analysis environment that supports schematic cross-probing between logic and physical models.

Encounter Diagnostics is available in two offerings:

• Encounter Diagnostics L (Basic) for precision-based bring-up applications
• Encounter Diagnostics XL (Volume and Precision Diagnostics Engine Pack), which offers four diagnostics engines and adds volume analysis and enhanced navigation capabilities

Benefits

• Uses a single, unified engine for precision and volume diagnostics
• Identifies the most critical yield-limiting design process issues
• Locates root cause defects with 80% or greater accuracy
• Isolates faults efficiently with bi-directional cross-probing between logic and physical models
• Enables physical design browsing to extract physical attributes and further localize yield limiters
• X-Y-Z location reporting of suspected defects maximizes the effectiveness of physical failure analysis lab equipment
• Analyzes thousands of failed devices quickly
• Universal ATPG vector support enables easy integration with any flow
• Patented pattern fault modeling optimizes 65nm, 45nm, and 32nm defect identification
• Increases the value of your existing automated yield learning system
• Offers a scalable solution that uses multiple processors or servers and a robust SQL-compatible database
• Offers a complete tool kit of algorithms and heuristics for detecting the most challenging design process defects
• Identifies scan-chain defects
• Locates failures in customer field returns