| Assura Physical Verification |
设计规则检测与版图和逻辑设计一致性检测，为SoC设计提供高良率的定制IP。 |
否
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| Cadence Litho Electrical Analyzer |
根据真实光刻轮廓线来抽取器件和连线的电气参数。分析并且修复由于系统性变量产生的时序和漏电流热点。 |
否
|
| Cadence Litho Physical Analyzer |
识别并修正光刻图形的热点。使用基于模型的技术快速并且准确地预测芯片的光刻轮廓，改进参数良率和芯片性能。 |
否
|
| Cadence Physical Verification System |
在一种解决方案中提供从前端到后端设计，实现并且签收的整个流程。加快设计规则检测和版图与逻辑设计一致性验证的周期。 |
否
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| Cadence QRC Extraction |
快速并且准确的对整个芯片进行抽取和分析。加速时序收敛并实现高质量的芯片。 |
否
|
| Cadence RF Design Methodology Kit |
Delivers verified methodologies packaged in a system-to-tapeout RFIC design flow, demonstrated on a segment representative design. |
否
|
| Virtuoso Accelerated Parallel Simulator |
Delivers scalable performance and capacity at full Spectre-level accuracy across a broad range of complex analog, RF, and mixed-signal blocks and subsystems. |
否
|
| Virtuoso AMS Designer |
Provides an advanced mixed-signal simulation solution for design and verification of analog, RF, memory, and mixed-signal SoCs. |
否
|
| Virtuoso Analog Design Environment |
Provides a comprehensive array of capabilities for electrical and statistical analysis, verification, and optimization of analog/mixed-signal designs, including the interfaces to many industry-standard simulators. |
否
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| Virtuoso Layout Migrate |
Offers rapid physical layout migration, including support for complex design rules at advanced nodes. |
否
|
| Virtuoso Layout Suite |
Provides the complete physical layout environment of the industry-standard Virtuoso custom design platform, a comprehensive solution for front-to-back custom-analog, digital, RF, and mixed-signal design. |
否
|
| Virtuoso Multi-Mode Simulation |
Enables comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle. |
否
|
| Virtuoso Schematic Editor |
Provides a complete design and constraint composition environment for front-to-back analog, custom-digital, RF, and mixed-signal designs. |
否
|
| Virtuoso Spectre Circuit Simulator |
Delivers a fast, SPICE-accurate simulator for challenging analog, RF, and mixed-signal circuit simulation and device characterization. |
否
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