开发工具/系统-定制IC设计-Cadence Space-Based Router

描述
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Growing design complexity and more digital and analog/mixed-signal content mean designers face critical yield and manufacturability challenges, such as lithography issues, inconsistent manufacturing rules, copper materials, electrical concerns, and performance requirements. Cadence® Space-Based Router addresses all these concerns simultaneously, helping designers achieve shorter time to convergence, better quality of silicon, and differentiated products for consumer and wireless markets.

Features/Benefits

High capacity easily handles flat and hierarchical data for 250K net designs
High-performance multi-threaded implementation accelerates completion of the largest designs
Innovative hierarchical, 3-D, space-based architecture enables accurate modeling, manipulation, and checking of sophisticated geometries and constraints for sub-65nm interconnect design closure
Signoff-quality advanced design-rule interconnect checking system delivers correct-by-construction design closure

文档(Document)

序号	PDF	描述
1	Cadence Space-based Router Datasheet	Cadence Space-based Router Datasheet
2	Virtuoso Custom Design Demo: High-performance Custom Routing and DFM Optimization for Advanced Proce	Virtuoso Custom Design Demo: High-performance Custom Routing and DFM Optimization for Advanced Process Nodes using the Cadence Space-based Router and Chip Optimizer

Cadence Space-Based Router

Features/Benefits

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