Cadence Low-Power Methodology Kit |
Cadence |
将低功耗技术流程组成一个有机的系统,并优化其具体应用于。从而通过完整的前端到后端方法学,最佳的实践,检测表和参考流程来消除低功耗设计的风险。 |
逻辑设计
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Cadence Low-Power Methodology Kit |
Cadence |
将低功耗技术流程组成一个有机的系统,并优化其具体应用于。从而通过完整的前端到后端方法学,最佳的实践,检测表和参考流程来消除低功耗设计的风险。 |
数字实现
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Cadence MaskCompose Reticle and Wafer Synthesis Suite |
Cadence |
Automates and optimizes reticle and wafer synthesis to eliminate errors and reduce mask-making cycle times. |
可制造性签收
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Cadence OrCAD Capture / Capture CIS |
Cadence |
Offers full-featured schematic editing of complex designs through hierarchical and variant design capabilities for fast, intuitive design capture. Robust component information system (CIS) promotes use of preferred, current parts to accelerate design capt |
PCB设计
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Cadence OrCAD FPGA System Planner |
Cadence |
The OrCAD FPGA System Planner offers technology for FPGA-PCB co-design that allows users to automatically create an optimum placement-aware initial pin assignment for an FPGA. |
PCB设计
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Cadence OrCAD PCB Designer |
Cadence |
Offers a proven, scalable, easy-to-use PCB editing and routing solution. Delivers a comprehensive feature set and seamless PCB design environment to take designs from concept to production. |
PCB设计
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Cadence OrCAD PCB SI |
Cadence |
Provides detailed interconnect modeling and electrical analysis. Enables pre- and post-layout signal integrity analysis at any stage. |
PCB设计
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Cadence Physical Verification System |
Cadence |
在一种解决方案中提供从前端到后端设计,实现并且签收的整个流程。加快设计规则检测和版图与逻辑设计一致性验证的周期。 |
数字实现
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Cadence Physical Verification System |
Cadence |
在一种解决方案中提供从前端到后端设计,实现并且签收的整个流程。加快设计规则检测和版图与逻辑设计一致性验证的周期。 |
定制IC设计
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Cadence Physical Verification System |
Cadence |
在一种解决方案中提供从前端到后端设计,实现并且签收的整个流程。加快设计规则检测和版图与逻辑设计一致性验证的周期。 |
射频集成电路设计
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Cadence Physical Verification System |
Cadence |
在一种解决方案中提供从前端到后端设计,实现并且签收的整个流程。加快设计规则检测和版图与逻辑设计一致性验证的周期。 |
可制造性签收
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Cadence PSpice A/D and Advanced Analysis |
Cadence |
Simulates analog/mixed-signal circuits quickly and completely to improve productivity and data integrity. Advanced Analysis prevents board failures by determining which components are over-stressed using Smoke analysis or by observing component yields usi |
PCB设计
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Cadence QRC Extraction |
Cadence |
快速并且准确的对整个芯片进行抽取和分析。加速时序收敛并实现高质量的芯片。 |
数字实现
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Cadence QRC Extraction |
Cadence |
快速并且准确的对整个芯片进行抽取和分析。加速时序收敛并实现高质量的芯片。 |
定制IC设计
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Cadence QRC Extraction |
Cadence |
快速并且准确的对整个芯片进行抽取和分析。加速时序收敛并实现高质量的芯片。 |
射频集成电路设计
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Cadence QuickView Layout and Manufacturing Data Viewer |
Cadence |
Allows engineers to view and superimpose manufacturing data in various industry-standard formats. |
可制造性签收
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Cadence RF Design Methodology Kit |
Cadence |
Delivers verified methodologies packaged in a system-to-tapeout RFIC design flow, demonstrated on a segment representative design. |
射频集成电路设计
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Cadence SiP Co-Design |
Cadence |
Flexible chip-package co-design methodologies with supporting utilities allow for customizable co-design flows that meet the organizational challenges associated with collaboration between chip and package design teams that may be globally distributed. |
IC 封装和SiP设计
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Cadence SiP Digital Architect |
Cadence |
Enables experimentation at the initial design stages for maximum functional density and performance. Evaluates tradeoffs and provides co-design optimization of IC I/O padring/array. Optimized for co-design with Encounter Digital Implementation System. |
IC 封装和SiP设计
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Cadence SiP Digital SI |
Cadence |
Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects. |
IC 封装和SiP设计
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