开发工具/系统-IC 封装和SiP设计-Cadence SiP Digital SI

品牌：Cadence

描述：Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded

包装：

封装：

无铅情况/ROHS：有铅

类别：IC 封装和SiP设计

经营商：科通芯城自营

Reads/writes Cadence SiP Layout files
Streamlines virtual prototyping, interconnect exploration, analysis, and modeling
Provides fast, high-capacity simulation for multi-gigahertz interconnect analysis
Performs topology editing and solution space exploration
Includes SPICE-based simulation
Provides embedded integration with partner supplied 3D field solvers
Provides hierarchical constraint management
Enables virtual substrate editing and post-layout debugging
Simplifies design debug and reviews with Cadence 3D Design Viewer

序号	PDF	描述
1	Automated Parasitic Backannotation and Testbench Generation for Verification of RF SiP Designs	Automated Parasitic Backannotation and Testbench Generation for Verification of RF SiP Designs
2	Cadence RF Design Methodology Kit Datasheet	Cadence RF Design Methodology Kit Datasheet
3	Cadence SiP Digital Design Datasheet	Cadence SiP Digital Design Datasheet
4	Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation	Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation
5	Modeling and Analysis Methodologies of Complex Digital System-in-Package Designs	Modeling and Analysis Methodologies of Complex Digital System-in-Package Designs