Cadence^® SiP Digital Architect manages the conceptual design flow from die to system-level SiP. It integrates with Encounter^® digital design databases in a bi-directional flow for co-design optimization. SiP Digital Architect makes it possible to rapidly author a system-level SiP connectivity model for feasibility and verification studies. This enables engineers to maximize the functional density and performance of the package, and to minimize power consumption. SiP Digital Architect also performs IC I/O padring/array co-design with optimization capabilities at the IC, substrate, and system levels.

Features/Benefits

• Speeds connectivity authoring and management with unique table and spreadsheet environment
• Integrates with Encounter digital IC design technologies
• Enables rapid system-level connectivity capture and “what-if” scenarios
• Resolves design tradeoffs early in the flow for maximum performance
• Completes I/O padring/array co-design with multi-level optimization
• Supports bi-directional ECO and LVS flow for full co-design implementation
• Performs feasibility and verification studies for design optimization
• Allows RF and mixed-signal incorporation as hierarchical sub-blocksprofiles