开发工具/系统

方案关键器件表：

型号	品牌	产品描述	类型
Windows Embedded Automotive	Microsoft	针对通信、娱乐、导航和连通服务，通过这一可扩展的创新平台实现丰富的车载体验。	Windows Embedded
Windows Embedded Device Manager 2011	Microsoft	通过扩展 System Center Configuration Manager 2007 的功能，使企业能够部署、评估和更新 Windows Embedded 设备，提供了一种单一管理解决方案，从而可以增强对 IT 基础结构及系统的了解和控制。	Windows Embedded
Windows Embedded Enterprise	Microsoft	使用 Windows 桌面操作系统的完整功能版本，为需要 Windows 应用程序兼容性和自定义用户界面的一系列专用互连设备提供支持。	Windows Embedded
Windows Embedded Handheld 6.5	Microsoft	使用基于 Windows Mobile 6.5 的这一标准软件平台，为零售、现场移动、交通以及医疗保健开发耐用移动设备	Windows Embedded
Windows Embedded POSReady 7	Microsoft	适用于寻求将店内交易处理设备发展到可增强客户体验和提升客户忠诚度的尖端 Point of Service 设备的零售企业。	Windows Embedded
Windows Embedded Thin Client	Microsoft	使用强大、熟悉、可靠的 Windows 操作系统将下一代瘦客户端设备更快推向市场。	Windows Embedded
ActiveParts Portal	Cadence	Component Search … Save … Place	OrCAD 产品
Allegro AMS Simulator	Cadence	Delivers advanced simulation capabilities for analog/mixed-signal development. Provides design entry feedback, component modeling, stress analysis, and yield projections.	PCB设计
Allegro Design Authoring	Cadence	Provides a multi-style logic authoring-driven, constraint-driven flow. Manages design constraints, net classes, buses, extended nets, and differential pairs.	PCB设计
Allegro Design Entry Capture / Capture CIS	Cadence	Enables rapid, intuitive schematic editing and hierarchical design with optimized sharing and reuse of components and subassemblies. Automates integration of field programmable gate arrays (FPGAs) and programmable logic devices (PLDs).	PCB设计
Allegro Design Publisher	Cadence	Converts Allegro Design Authoring schematics and Allegro PCB Designer PCBs to content-rich PDFs?creating a secure, single-file representation of the design.	PCB设计
Allegro Design Workbench	Cadence	Provides a collaborative environment that integrates design tools, library development and distribution, data management, and process control?all aimed at increasing productivity, reducing errors, and eliminating redundancy.	PCB设计
Allegro FPGA System Planner	Cadence	The Allegro FPGA System Planner offers a complete, scalable technology for FPGA-PCB co-design that allows users to automatically create an optimum placement-aware initial pin assignment for one or more FPGAs.? It also allows users to optimize pin assignme	PCB设计
Allegro Package Designer	Cadence	Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Optimized for single die or side by side die designs.	IC 封装和SiP设计
Allegro Package SI	Cadence	Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions.	IC 封装和SiP设计
Allegro PCB Designer	Cadence	Speeds designs from placement and routing through to manufacturing with powerful features such as design partitioning, RF design capabilities, and interconnect design planning. Production-proven to increase productivity and help engineers quickly ramp up	PCB设计
Allegro PCB Librarian	Cadence	Significantly accelerates creation and validation of schematic, PCB footprint and digital simulation map files. This enables librarians, engineers and/or designers to reduce development time for high-pin-count devices from days to minutes.	PCB设计
Assura Physical Verification	Cadence	设计规则检测与版图和逻辑设计一致性检测，为SoC设计提供高良率的定制IP。	数字实现
Assura Physical Verification	Cadence	设计规则检测与版图和逻辑设计一致性检测，为SoC设计提供高良率的定制IP。	定制IC设计
Assura Physical Verification	Cadence	设计规则检测与版图和逻辑设计一致性检测，为SoC设计提供高良率的定制IP。	射频集成电路设计

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