Cadence® Litho Electrical Analyzer is a complete and silicon-correlated electrical DFM analyzer that allows designers using sub-90nm processes to optimize and control the impact of lithography, mask, etch, RET, OPC, and CMP effects on chip parameters. It plugs directly into the designer’s existing flows for IP, custom analog, and cell-based digital designs.

Cadence Litho Electrical Analyzer uses fab-certified technology to predict contours across the process window and to predict device and interconnect electrical behavior. Its silicon contour-based analysis technology provides an accurate model-based solution to identify parametric issues associated with manufacturing variability. Therefore, designers can analyze and minimize the effects of variations on design performance and improve yield.

Features/Benefits

• Extracts device and interconnect electrical behavior from contours
• Detects and repairs timing and leakage hotspots due to systematic variations
• Reduces design margins and accelerates timing closure
• Integrates with most library, custom, and chip design flows
• Allows designers to optimize electrical parameters on-the-fly without any change to their library layout characterization
• Integrates with Cadence Litho Physical Analyzer to deliver accurate full-chip contour shape predictions in a matter of hours
• Integrates with Cadence QRC Extraction and Encounter® Timing System