Allegro AMS Simulator

品牌:Cadence
描述:Delivers advanced simulation capabilities for analog/mixed-signal development. Provides design entry
包装:
封装:
无铅情况/ROHS: 有铅
类别:PCB设计
经营商:科通芯城自营


Cadence® Allegro® AMS Simulator includes PSpice® technology at the core, providing fast and accurate simulations. This Advanced Analysis package includes utilities for sensitivity analysis, goal-based multi-parameter optimization, component stress and reliability analysis, and Monte Carlo analysis for yield estimation. The parametric plotter analyzes interdependence among parameters and converts simulation data into meaningful results. When combined with , the schematics drawn in AMS Simulator can also drive PCB layout—significantly reducing design time and eliminating redrawing errors. It includes a large library of known models and behavioral modeling techniques that make refining the analog/digital interface a straightforward task.

Features/Benefits
  • Provides fast, accurate analysis of analog and mixed-signal designs
  • Integrates seamlessly with Allegro Design Entry HDL
  • Performs AC, DC, noise, transient, and parameter sweep analyses
  • Includes magnetic parts editor for transformer and inductor design
  • Utilizes a large inventory of accurate internal models with temperature effects
  • Describes functional blocks using editable behavioral models
  • Includes library of more than 20,000 known devices and components
  • Provides automatic circuit optimizer to increase performance
  • Performs circuit sensitivity, component stress, and productive yield analyses
  • Interfaces with MATLAB Simulink for advanced electrical modeling

文档(Document)

序号 PDF 描述
1 32bit MCU Full-Chip Verification using AMS Verification Flow (AMSVF)     32bit MCU Full-Chip Verification using AMS Verification Flow (AMSVF)
2 Cadence Allegro System Interconnect Design Platform Brochure     Cadence Allegro System Interconnect Design Platform Brochure
3 Cadence Simulation for PCB Design Datasheet     Cadence Simulation for PCB Design Datasheet
4 Detecting and Managing Device Reliability in Block-level and Chip-level Simulations     Detecting and Managing Device Reliability in Block-level and Chip-level Simulations
5 Dynamic IR-Drop Analysis with VoltageStorm DG Using Different Power Grid Views for Cell Modeling     Dynamic IR-Drop Analysis with VoltageStorm DG Using Different Power Grid Views for Cell Modeling
6 Ensuring Reliable and Optimal Analog PCB Designs with Allegro AMS Simulator     Ensuring Reliable and Optimal Analog PCB Designs with Allegro AMS Simulator
7 Full-Chip Verification Flow with Third-Party IP Using AMS Methodology     Full-Chip Verification Flow with Third-Party IP Using AMS Methodology
8 Modeling Analog Circuits with Routed Interconnect using AMS and Allegro SI     Modeling Analog Circuits with Routed Interconnect using AMS and Allegro SI

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