| Parameter |
Value |
| Voltage |
1.8V±0.1V |
| Package |
WBGA 60 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant |
| Status |
P |
| CL-tRCD-tRP |
5-5-5 |
| CL-tRCD-tRP |
5-5-5/6-6-6 |
| CL-tRCD-tRP |
7-7-7 |
| Organization |
64Mbitx8/4 Banks |
| RoHS |
Y |
| Speed Grade |
DDR2-1066//-18 |
| Speed Grade |
DDR2-667//-3 |
| Speed Grade |
DDR2-800//-25/25I |
| Organization |
64Mbitx8 |
| Voltage |
1.8V±0.1V |
| Speed |
7/7/7,5-5-5/6-6-6,5/5/5 |
| Package |
WBGA 60 Ball (8X12.5 mm²), using Lead free materials with RoHS compliant |
| Status |
P |
| RoHS |
Y |
Description
The W9751G8JB is a 512M bits DDR2 SDRAM, and speed involving -18/-25/25I/-3. Status: Mass Production
Features
Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data?
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)?
Data masks (DM) for write data?
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)?
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts?
Auto Refresh and Self Refresh modes?
Precharged Power Down and Active Power Down?
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)?
Interface: SSTL_18
文档(Document)
