Cadence® Incisive® Enterprise Specman Elite® Testbench uses executable specifications and designer-specified constraints to automate testbench generation, while simultaneously detecting misrepresentations of the specification. Its automated data and assertion checking speeds debug, while its functional coverage analysis capability drives verification using the metric-driven verification methodology.

Specman technology supports industry-standard verification languages and is compatible with the Open Verification Methodology (OVM), the (UVM), and the Reuse Methodology (RM), so you can quickly and easily integrate it with established verification flows. It also provides an environment for working with, compiling, and debugging testbench environments written in the language. With automated testbench generation, you can boost verification productivity at block, chip, and system levels.

To simulate an testbench with a design written in VHDL/Verilog, the Specman tool must be run in conjunction with a separate HDL simulator. While it supports co-simulation with industry-standard simulators such as Synopsys VCS or Mentor Questa, Specman technology is used most commonly with , where tighter product integration offers faster runtime performance and additional debug capabilities.

Specman Advanced Option

Available as an add-on to the Specman simulator, the Specman Advanced Option combines dynamic loading and reseeding techniques (both available in ) to greatly boost verification and debug productivity. Users can run a simulation up to a certain point, save its state, and resume it in multiple processes later on. Simulation states can be restored and reseeded to increase coverage, and new files can be dynamically loaded after restoring to guide future results.

Bypassing lengthy start-up functionality, the Specman Advanced Option allows users to quickly locate the most meaningful portion of their simulations; achieve higher functional coverage; reduce test development and debug cycles; reduce regression runs; and save hundreds of simulation hours.

Features/Benefits

• Captures executable specifications to eliminate misrepresentations that lead to bug escapes
• Leverages the e language’s unique aspect-oriented programming (AOP) capabilities for rapid environment construction, scalability, and reuse
• The “IntelliGen” AOP constraint solver automates test generation with up to 5x faster runtime, unprecedented distribution control, and scalability for more than 1 billion logic gate devices
• Automates data and assertion checking for faster debug
• Tracks industry-standard coverage metrics (functional, transactional, HDL) for higher verification quality
• Supports a proven metric-driven verification solution that applies UVM-MS for digital-centric mixed-signal verification to achieve first-pass success
• Creates reusable sequences and multi-channel virtual sequences on top of an e verification environment
• Comprehensive language support includes e, Open Verification Library (OVL), OVM class library, UVM class library, SystemC?, SystemVerilog, Verilog, VHDL, PSL, SVA, C/C++ models, MATLAB models, and analog models in Verilog-A, VHDL-A, wreal, and SPICE
• Works with all major simulators, with a high-speed direct kernel interface when used inside Incisive Enterprise Simulato