Development Tools / System-IC Packaging and SiP Design-

brand：Cadence

Description：Delivers a single schematic and simulation solution for RF/analog ICs and complex IC package substra

Packaging：

Lead-free status/ROHS： Yes

Category：IC Packaging and SiP Design

Seller：科通芯城自营

No.	PDF	Description
1	Automated Parasitic Backannotation and Testbench Generation for Verification of RF SiP Designs	Automated Parasitic Backannotation and Testbench Generation for Verification of RF SiP Designs
2	Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation	Interview: SiP16.0 extends RFSiP Implementation to Parasitics/Simulation
3	Modeling and Analysis Methodologies of Complex Digital System-in-Package Designs	Modeling and Analysis Methodologies of Complex Digital System-in-Package Designs
4	Use of System Link Design for Multi-Board Systems	Use of System Link Design for Multi-Board Systems