Development Tools / System-IC Packaging and SiP Design-

Description
Document

Cadence® SiP Layout is the physical co-design and place-and-route solution for complex 3D SiP package design. Supporting all package interconnect strategies and combinations, SiP Layout provides constraint-driven layout of the package substrate. Since it must operate in a 3D world, SiP Layout allows stack assembly optimization with 3D layout and editing. It also performs autoroute and breakout on flip-chip dies to reduce time-consuming and tedious manual breakout. Comprehensive DFM checking and modification improve substrate yield. Design review documentation and debug, followed by direct manufacturing tapeout, complete the package.

Features/Benefits

Provides 3D die stack creation/editing for rapid stack assembly and optimization
Completes I/O padring/array co-design with multi-level optimization
Enables connectivity assignment to minimize layer usage based on SI analysis
Includes solid model 3D design viewer with snapshots for design review
Performs 3D wirebond verification and DRC
Supports bi-directional ECO and LVS flow for full co-design environment profiles
Includes a comprehensive suite of DFM preparation technologies
Supports highly integrated (Encounter) and distributed (die abstract with Encounter or Virtusoso) co-design methodologies to match your chip-package design environments

文档(Document)

No.	PDF	Description
1	Cadence Chip-Package-Board Co-Design Solution Datasheet	Cadence Chip-Package-Board Co-Design Solution Datasheet
2	Cadence RF Design Methodology Kit Datasheet	Cadence RF Design Methodology Kit Datasheet
3	Cadence SiP Digital Design Datasheet	Cadence SiP Digital Design Datasheet

Cadence SiP Layout

Features/Benefits

文档(Document)

PRODUCTS

SOLUTIONS

NEWS

ABOUT US