| 参数 |
数值 |
| Voltage |
2.5V ±0.2V |
| Package |
Packaged in 60 Ball TFBGA, using lead free materials with RoHS compliant |
| Status |
P |
| Organization |
16Mbitx16/4 Banks |
| RoHS |
Y |
| Speed Grade |
CL3//-5/-5I/200 MHz |
| Organization |
16Mbitx16 |
| Voltage |
2.5V ±0.2V |
| Speed |
(-5/-5I)_200MHz_CL3 |
| Package |
Packaged in 60 Ball TFBGA, using lead free materials with RoHS compliant |
| Status |
P |
| RoHS |
Y |
Description
The W9425G6JB is a 256M DDR SDRAM and speed involving -5/-5I Status:
Features
2.5V ±0.2V Power Supply?
Up to 200 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle?
Differential clock inputs (CLK and /CLK)
DQS is edge-aligned with data for Read; center-aligned with data for Write?
CAS Latency: 2, 2.5 and 3
Burst Length: 2, 4 and 8?
Auto Refresh and Self Refresh?
Precharged Power Down and Active Power Down?
Write Data Mask?
Write Latency = 1
7.8μS refresh interval (8K/64 mS Refresh)
Maximum burst refresh cycle: 8?
Interface: SSTL_2?
文档(Document)
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