| 参数 |
数值 |
| Voltage |
2.5V ±0.2V |
| Voltage |
2.6V ±0.1V |
| Package |
Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant |
| Status |
NRFND |
| Organization |
16Mbitx16/4 Banks |
| RoHS |
Y |
| Speed Grade |
CL2.5//-6/-6I/166 MHz |
| Speed Grade |
CL3//-4/250 MHz |
| Speed Grade |
CL3//-5/-5I/200 MHz |
| Organization |
16Mbitx16 |
| Voltage |
2.6V ±0.1V 2.5V ±0.2V |
| Speed |
-4_250MHz_CL3, -5/-5I_200MHz_CL3, -6/-6I_16MHz_CL2.5 |
| Package |
Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant |
| Status |
NRFND |
| RoHS |
Y |
Description
The W9425G6EH is a 256M DDR SDRAM and speed involving -4/-5/-5I/-6/-6I Status: Not recommended for new design.
Features
2.5V ±0.2V Power Supply for DDR333/400
2.6V ±0.1V Power Supply for DDR500
Up to 250 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and /CLK)
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5, 3 and 4
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
7.8μS refresh interval (8K/64 mS refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2
文档(Document)
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