参数 |
数值 |
Voltage |
2.4V~2.7V |
Voltage |
2.5V±0.2V |
Package |
Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant |
Status |
P |
Organization |
4Mbitx16/4 Banks |
RoHS |
Y |
Speed Grade |
CL3//-5/-5I/200 MHz |
Speed Grade |
CL3/CL4//-4/250 MHz |
Description
W9464G6JH is a 64M DDR SDRAM and speed involving -4 / -5 and -5I Status: Mass Production
Features
2.5V ±0.2V Power Supply for DDR400
2.4V~2.7V Power Supply for DDR500
Up to 250 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and /CLK)
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5, 3 and 4
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
15.6μS refresh interval (4K/64 mS Refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2