开发工具/系统-定制IC设计-Virtuoso UltraSim Full-Chip Simulator

描述
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The Cadence® Virtuoso® UltraSim Full-Chip Simulator is a high-performance transistor-level FastSPICE circuit simulator for verifying large custom, analog/mixed-signal, RF, memory and SoC designs. It uses true hierarchical simulation with patented isomorphic and adaptive partitioning algorithms to provide the capacity, accuracy, and speed required for design and verification, regardless of design type or stage in the design cycle.

Features/Benefits

Accelerates pre-and post-layout simulation for a wide range of applications from blocks to full-chip SoCs
- Basic and advanced circuit diagnostics
- Advanced parasitic reduction algorithm
- Advanced algorithm for custom digital verification
Offers design verification flexibility through various modes
Delivers silicon-accurate simulation
Has the flexibility to switch between environments for different design stages via integration with Virtuoso Analog Design Environment
Delivers high analog capacity and simulation speed for AMS simulation solutions for block authoring and final verification

文档(Document)

序号	PDF	描述
1	An Effective EM/IR-Drop Flow with UltraSim and VoltageStorm/ ElectronStorm Options	An Effective EM/IR-Drop Flow with UltraSim and VoltageStorm/ ElectronStorm Options
2	Cadence and Multigig Success Story	Cadence and Multigig Success Story
3	Cadence and Realtek Success Story	Cadence and Realtek Success Story
4	Cadence and Teradyne Success Story	Cadence and Teradyne Success Story
5	Cadence Virtuoso Custom Design Platform Brochure	Cadence Virtuoso Custom Design Platform Brochure
6	Netlist Based IR Drop & Electromigration Analysis Flow In Virtuoso Ultrasim	Netlist Based IR Drop & Electromigration Analysis Flow In Virtuoso Ultrasim
7	Speed Up RF Mixed-Signal Simulation Using Novel Hierarchical Fast Envelope Simulation	Speed Up RF Mixed-Signal Simulation Using Novel Hierarchical Fast Envelope Simulation
8	UltraSim Netlist-Based Memory EMIR Flow	UltraSim Netlist-Based Memory EMIR Flow
9	Use of AMS Verification Flow for Battery Management Design Simulations	Use of AMS Verification Flow for Battery Management Design Simulations
10	Using Advanced Low-power Techniques to Mitigate Headaches, an interview	Using Advanced Low-power Techniques to Mitigate Headaches, an interview
11	Virtuoso Custom Design Demo: Solving D/MS Design Challenges with Virtuoso AMS Designer	Virtuoso Custom Design Demo: Solving D/MS Design Challenges with Virtuoso AMS Designer
12	Virtuoso Multi-Mode Simulation Datasheet	Virtuoso Multi-Mode Simulation Datasheet

Virtuoso UltraSim Full-Chip Simulator

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