Virtuoso Power System provides a convergent power and signal integrity analysis and signoff solution that validates the power intent of a design. It supports distributed power consumption, power-rail IR drop, power-rail electromigration, and signal-net electromigration analysis and signoff.

Virtuoso Power System can be used within the design implementation flow to enable signoff-accurate validation of blocks, or as a pre-tapeout full-chip signoff solution. When used within a custom design methodology, Virtuoso Power System ensures a predictable, more convergent flow through tapeout.

Using abstract modeling, Virtuoso Power System integrates with Cadence Encounter Power System to deliver a comprehensive, full-chip signoff solution for the largest system-on-chip designs.

Designed for optimal usability, accuracy, and runtime, Virtuoso Power System is tightly integrated with the Virtuoso platform and enables designers to rapidly check that power rails can supply the amount of power needed by the design, within the context of the package and board.

Features/Benefits

• Tightly integrated with the Virtuoso platform and custom design methodology
• Delivers consistent, integrated power and IR-drop analysis across the implementation flow, from floorplanning through optimization and signoff
• Provides a comprehensive, hierarchical full-chip solution
• Utilizes standard extraction and simulation engines for accurate and convergent results
• Boosts productivity and delivers predictable tapeout schedules