Palladium Dynamic Power Analysis

品牌:Cadence
描述:将cadence Palladium 加速仿真技术扩展到系统级动态功耗分析 (DPA)。通过运行Palladium仿真器,工程师不但可以利用真实的系统环境来分析员软件,而且可以通过DPA技术来优化功耗
包装:
封装:
无铅情况/ROHS: 有铅
经营商:科通芯城自营


Cadence® Palladium® Dynamic Power Analysis (DPA) uniquely enables engineers using emulation to also analyze software in a system-level environment. The solution’s ability to run various design or implementation scenarios--and determine their impact on power dissipation under a realistic application environment--is vital to striking a balance between power budget and expected performance. Additionally, the solution delivers power calculation by capturing the necessary power activities in a common DPA power database. This capability further enables the sharing of verification resources while DPA is computing the power profile offline.

Features/Benefits
  • Supports both RTL and gate-level power estimation
  • Enables high-performance system-level power estimation to identify peaks and calculate averages on long runs
  • Realistic in-circuit emulation environment allows users to estimate power under real operating conditions
  • Detailed analysis helps users identify where analysis is needed
  • Enables relative compare of IP at the RTL phase to identify architectural issues and offer HW/SW trade-offs
  • Reduces packaging cost and helps to avoid costly respins
  • Supports the Common Power Format (CPF)

文档(Document)

序号 PDF 描述
1 Cadence Palladium Dynamic Power Analysis Datasheet     Cadence Palladium Dynamic Power Analysis Datasheet
2 Power-Aware Verification Spans IC Design Cycle White Paper     Power-Aware Verification Spans IC Design Cycle White Paper

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