Cadence® Encounter® True-Time ATPG offers robust automated test pattern generation (ATPG) engines that generate tests for all standard design-for-test (DFT) methods and flows. It provides intelligent ATPG with compression to reduce scan test time while maintaining the highest test coverage. With its onboard timing-aware and power-aware engine, and by using circuit timing information, True-Time ATPG supports both stuck-at and transition fault models and automatically generates high-coverage static and timing-accurate delay test patterns to uncover small delay defects in deep submicron designs.

True-Time ATPG’s patented pattern fault technology raises the bar in fault detection by providing advanced modeling capabilities (including RAM modeling) for proven pass-through test and defect-based modeling. Its gate-exhaustive coverage (GEC) model and pattern generation methodology is superior to N-Detect methods in both efficiency and effectiveness (production-proven) for capturing gate-intrinsic defects. Its low-power test capability minimizes the costly impact of average and instantaneous test-mode power consumption on yield and product reliability.

True-Time ATPG is available in Basic and Advanced configurations.

Benefits

• Ensures high quality of shipped silicon with production-proven 2-4x reduction in test escapes
• Provides superior partial scan coverage with proprietary pattern fault modeling and sequential ATPG algorithms
• Optimizes test coverage with RRFA and DFA test point insertion methodology
• Boosts productivity by integrating with Encounter RTL Compiler
• Delivers superior runtime throughput with high-performance model build and fault simulation engines as well as distributed ATPG
• Lowers cost of test with pattern compaction and compression techniques that maintain full scan coverage
• Balances tester costs with diagnostics methodologies by offering flexible compression architectures with full X masking capabilities (including OPMISR+ and XOR-based solutions)
• Supports low pin-count testing via JTAG control of MBIST and high-compression ratio technology
• Supports reduced pin-count testing for I/O test
• Interfaces with Encounter Power System for accurate power calculation and pattern IR drop analysis
• Reduces circuit and switching activity during manufacturing test to manage power consumption
• Reduces false failures due to voltage drop
• Provides a GUI with powerful interactive analysis capabilities including a schematic viewer and sequence analyzer