Development Tools / System-Logic Design-

Description
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Decisions made during the architectural planning stages of the design cycle largely determine the chip’s resulting size, power consumption, performance, and cost. It’s during these early stages that design teams can realize the biggest benefits by considering and quantifying a variety of architectural options.

Cadence® InCyte Chip Estimator provides a cockpit-style environment with integrated estimation models for common foundries and IP providers, enabling rapid what-if analysis across the design solution space. Whether design teams are looking at size, power, and performance tradeoffs, low-power planning, economic analysis, or simply IC design feasibility, InCyte Chip Estimator provides an intuitive, easy-to-use environment where users don’t have to be IC design experts to achieve accurate results. And with its strong connection to IC implementation technologies (such as the ), InCyte Chip Estimator allows users to export their design intent downstream and ultimately converge on size, power, performance, and cost expectations in final silicon.

Features/Benefits

Accurately estimates IC size, power, leakage, performance, and cost
Enables rapid what-if analysis across design architecture, IP, and manufacturing process options to optimize design specifications
Achieves die size and power reductions through architectural exploration
Generates complete IC economic analysis and budgetary quotes
Intuitive user interface makes it easy to use in engineering, marketing, field, and management organizations
Fast, accurate, and simple-to-use environment helps any user achieve optimal results without being an IC design expert
Includes an integrated catalog of thousands of analog, mixed-signal, and digital IP components from more than 185 suppliers through ChipEstimate.com
Supports estimations specific to leading foundry manufacturing processes
Enables pre-RTL power estimation, low-power planning, and CPF authoring and exploration
Assesses performance achievability in specific manufacturing processes with specific IP components

文档(Document)

No.	PDF	Description
1	Analyzing Die Size, Power and Cost Tradeoffs Between Different Cell Libraries for Mobile Application	Analyzing Die Size, Power and Cost Tradeoffs Between Different Cell Libraries for Mobile Applications
2	Archived webinar - Start Your Project in the Right Direction with Pre-RTL Power Exploration	Archived webinar - Start Your Project in the Right Direction with Pre-RTL Power Exploration
3	Cadence InCyte Chip Estimator Datasheet	Cadence InCyte Chip Estimator Datasheet
4	Chipestimate.com	Chipestimate.com
5	Closing the Chip Architecture Implementation Feedback Loop Technical Paper	Closing the Chip Architecture Implementation Feedback Loop Technical Paper

Cadence InCyte Chip Estimator

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